Review of MOS transistor structure and operation; overview of wafer processing and device implementation, layout and design rules. CMOS gate design; static and dynamic logic; modelling of transients and delays. Clocked circuits; interconnect effects, and I/O. Memory and programmable logic arrays. Technology scaling effects; design styles and flow. (Lec: 3, Lab: 0.25, Tut: 0)
Review of MOS transistor structure and operation; overview of wafer processing and device implementation, layout and design rules. CMOS gate design; static and dynamic logic; modelling of transients and delays. Clocked circuits; interconnect effects, and I/O. Memory and programmable logic arrays. Technology scaling effects; design styles and flow. (Lec: 3, Lab: 0.25, Tut: 0)
