Digital circuit design using verilog and logic synthesis, the electronic properties of logic gates, electrical interfacing between logic families, asynchronous to synchronous interfacing, clock distribution and timing, VLSI design options. Students implement substantial circuits with field- programmable gate arrays. Includes: Experiential Learning Activity Prerequisite(s): ELEC 2507 and ELEC 2607. Lectures three hours a week, laboratory three hours a week. [0.5 credits]
Digital circuit design using verilog and logic synthesis, the electronic properties of logic gates, electrical interfacing between logic families, asynchronous to synchronous interfacing, clock distribution and timing, VLSI design options. Students implement substantial circuits with field- programmable gate arrays. Includes: Experiential Learning Activity Prerequisite(s): ELEC 2507 and ELEC 2607. Lectures three hours a week, laboratory three hours a week. [0.5 credits]
